Mixed-signal circuits and data converters 
RF, mm-wave and THz circuits A fully integrated plasmonic logic implementation system integrates a plasmonic logic gate together with several necessary supporting blocks. Firstly, it requires an integrated excitation of plasmonic waves instead of coupling in plasmonic waves from an off-chip light source. Secondly, modulators responsible for Phase-Shift Keying the wave at high speeds are required. By using the plasmonic waveguide, plasmonic logic and PM-to-AM can be realized. Then, the detection of the output involves a photodetector, which produces an electrical signal proportional to the intensity of the incident plasmonic wave. Finally, a CMOS circuit is responsible for comparing the electrical signal from the photodetector to an adjustable threshold and capturing the resulting data in the digital domain. This digital data can be fed into another set of modulators for subsequent computations or can be considered as the output of the circuit. The circuit should be able to capture the data at a rate of up to 200−300 Gb/s, which is too challenging to do in current CMOS technology. So, we use IMEC IN5 FinFET technology, an advanced scale-down technology with a minimum finger width of 5nm. This research mainly focuses on the CMOS detector design, which includes the TIA, the comparator, and the output buffer.
