Mixed-signal circuits and data converters 
Quantum and cryogenic circuits Our wish: Quantum computers use quantum mechanical principles like superposition and entanglement to perform calculations in parallel on large amounts of data. This way, they promise significant speedups of complex algorithms. In a quantum computer, the classical binary bits are replaced by quantum particles (qubits) at extremely low cryogenic temperatures of a few mK. Interaction with these qubits requires conventional digital and analog control circuits. Today's control circuits operate at room temperature, requiring long cables to connect them to the qubits at cryogenic temperatures. This interconnection strategy is only feasible for a limited number of qubits, whereas practical quantum algorithms require thousands or even millions of qubits. Therefore, the control circuits should be placed close to the qubits to obtain a more scalable solution. Hence, they should also operate at cryogenic temperatures, typically on the 4.2 K stage of the cryostat.
Challenges: The cooling power at this 4.2 K stage is limited, which leads to a very stringent power budget for these control circuits. Furthermore, designers must deal with an increased threshold voltage, more flicker noise, and a larger variability. Finally, the absence of reliable cryogenic device models makes it hard to predict how the designed circuit will behave once it is cooled down to 4.2 K. Simply copying-paste room temperature design techniques to cryogenic temperatures will never yield the desired performance.
Our research: Besides these challenges, there are also some advantages. The higher carrier mobility leads to faster transistors, and the lower temperature leads to lower thermal noise. This work proposes the research by design methodology to iteratively explore which topologies and design techniques maximally benefit from the cryogenic environment. We focus on implementing high-speed data converters in standard CMOS at cryogenic temperatures (cryo-CMOS). The first prototype chip containing high-speed comparators was designed in 2022 and is currently under evaluation. A second prototype chip containing an ADC was designed in the summer of 2023.
