Mixed-signal circuits and data converters Our wish: The analog front-end (AFE) has become the dominant power bottleneck in modern signal acquisition chains, often overshadowing the ADC itself due to stringent gain and linearity requirements. To relax these AFE constraints, we need ADCs that offer significantly lower input-referred noise while maintaining high speed.
Furthermore, for applications like optical links and autonomous automotive sensors, this high performance must not come at the cost of delay; we require a minimal-latency architecture that avoids the throughput-latency trade-off of deep pipelining or heavy oversampling.
Challenges: Achieving low noise at high speeds (>100 MS/s) is notoriously difficult for power-efficient SAR-based architectures. As we push for faster bit trials and higher precision, reference settling and voltage ringing become critical issues that degrade precision. Additionally, traditional pipelining improves throughput but sacrifices system latency, creating a barrier for latency-critical applications.
Finally, the residue amplifier (RA) becomes a substantial power burden when both noise and latency are being minimized; while open-loop amplifiers are efficient, they are typically too sensitive to unsettled residue voltages to be viable in high-precision contexts.
Our research and results: We developed a two-stage SAR ADC that leverages asynchronous pipelining and novel domain-crossing RC reference snubbers to counter these trade-offs. The snubbers passively suppress ringing to enable a noise-efficient, open-loop floating-inverter residue amplifier (FIA-RA).
To summarize our results:
