Mixed-signal circuits and data converters Our wish: The latency of analog-to-digital converters (ADCs) has become a new critical aspect for some quickly evolving, modern applications. For example, this holds for wireline/optical links in data centers and fully autonomous cars. Any application with a short round-trip time or fast feedback loop will need a low-latency ADC. Therefore, we must steer away from traditional, heavily-pipelined ADCs.
Challenges: There is a great demand for high data throughput, good fidelity, and excellent ADC power efficiency. Especially above medium operation speeds, it becomes challenging to combine good power efficiency with low latency, partially due to the limits of the technology at hand. Only a handful of published works are in our target space at top conferences (see figure).
Ultimately, this means that the ADCs that cater to these evolving low-latency applications will be challenging to design for low power because the power burden (and bits) per ADC sub-stage will grow. In particular, the residue amplifier will significantly dominate the power consumption.
Our research: We designed a low-power, high-gain/precision residue amplifier to solve the above challenges. This residue amplifier will be employed in a Nyquist ADC with a minimal-latency architecture in the high-resolution, 100+ MS/s range. This prototype chip (see figure) was implemented throughout 2022-2023 and is currently being evaluated.
