Up until now, CMOS has been the preferred technology for wireless transceivers due to its low cost and high level of integration. Indium phosphide (InP)-based technologies however, offer higher output powers and a higher maximum oscillation frequency than the current state-of-the-art CMOS technologies. This indicates that InP-based technologies are more suitable for the next generation of cellular communication in which the operating frequency will be pushed beyond 100 GHz.
While several InP-based power amplifiers operating above 100 GHz have been demonstrated, they generally show poor power-added efficiency (PAE) at power backoff (PBO). This makes them unsuitable for implementation in mobile devices, where battery life is the main limitation. It also poses challenges for heat dissipation when used in phased array systems. This research focuses on the design of InP-based power amplifiers with high efficiency in the deep PBO region while still providing sufficient output power. This enables the use of higher-order modulation schemes. When combined with the large available bandwidth above 100 GHz these higher-order modulation schemes will enable data rates up to 100 Gbit/s.