Mixed-signal circuits and data converters Our wish: High-speed analog-to-digital converters (ADCs) are one of the most important building blocks enabling high-speed communication. Time-interleaved (TI) architectures are a popular solution for reaching sampling rates in the 10-100 GS/s range. We aim to further enhance the speed of these architectures by focussing on the design of the front end and clocking network, thereby improving data rates in wireline and optical communications.
Challenges: Designing analog front ends (AFE) and clocking networks to distribute the incoming signal and the sampling clock, respectively, comes with very difficult bandwidth and jitter requirements at high sample rates (>100 GS/s). This makes the power of AFE and clocking network non-negligible in TI-ADC designs. For this reason, some designs implement the AFE in a different manufacturing process (SiGe), followed by the deeply scaled CMOS used for the sub-ADCs, which simply kicks the problem further down the road. Using different processes also increases manufacturing costs, making these solutions not viable for high-bulk production.
Our Research: We plan on designing a 6-bit, >100 GS/s ADC in 7 nm FinFET, focusing on developing techniques that help alleviate the harsh bandwidth and jitter requirements.
