Mixed-signal circuits and data converters Research goal: Analog-to-digital converters (ADCs) are essential in mixed-signal integrated circuits. As the processing speed increases, single-channel ADCs will meet a fundamental limit in the trade-off between speed, resolution, and power. Using time-interleaved (TI) architectures is attractive when the sampling rate is above several GHz. However, interleave multiple sub-ADCs will inevitably cause channel-to-channel mismatches, such as offset, gain mismatch, timing skew and bandwidth mismatch. The goal of this project is to build up a prototype of a high-speed, high-linearity TI-ADC by various calibrations to remove the artifacts.
Gap in the SotA: Many calibration techniques have been recently published. One of them is blind digital calibration which corrects the mismatches in digital backend using auto-correlation algorithm [1]. This technique increases the circuits complexity and is very power-hungry. Another calibration is to align all sub-ADCs to a coarse reference ADC which is more energy-efficient, but it requires the reference ADC to run at full sampling rate, limiting the whole speed of TI-ADC [2].
Recent results: We propose a new TI architecture for a high-speed, medium-resolution TI-ADC. The linearity has been improved by: 1. A high-linearity input driver to suppress the 3rd and high-order distortion; 2. The artifacts are removed by various calibrations with better efficiency and without degrading the whole sampling rate. This prototype has been verified by architecture-level modeling and comprehensive transistor-level simulations. Measurement results are expected in the course of 2026.
[1] C. -E. Hsieh et al., "24.6 A Power- and Area-Efficient 4nm Self-Calibrated 12b/16GS/s Hierarchical Time-Interleaving ADC," 2025 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2025, pp. 438-440.
[2] J. Song, K. Ragab, X. Tang and N. Sun, "A 10-b 800-MS/s Time-Interleaved SAR ADC With Fast Variance-Based Timing-Skew Calibration," in IEEE Journal of Solid-State Circuits, vol. 52, no. 10, pp. 2563-2575, Oct. 2017.
