A high-speed, energy-efficient time-interleaved analog-to-digital converter

Research goal: Analog-to-digital converters (ADCs) are essential in mixed-signal integrated circuits. As the processing speed increases, single-channel ADCs still obey a fundamental trade-off between speed, resolution, and power. Using time-interleaved (TI) architectures is attractive when the sampling rate is above several GHz. However, time-interleaving increases the penalty of mismatch, gain error, time skew, and power consumption. Although advanced technology can relieve these issues, some new challenges, for example, the increase of flicker noise and bandwidth mismatch, pop up. This Ph.D. project aims to investigate and develop novel TI-ADC architectures that push the boundaries of the state-of-the-art at the resolution and speed frontiers.

Gap in the SotA: Chopping and auto-zeroing are widely used to reduce 1/f noise. However, it is challenging to implement them in high-frequency designs due to parasitics, mismatches of switches, etc. Currently, the state-of-the-art that implements chopping beyond 1 GHz usually adds dither simultaneously to calibrate the mismatch in the digital domain, significantly increasing the circuit's complexity. Moreover, the bandwidth mismatch severely deteriorates the performance of TI-ADCs, especially in a wide-band communication system. Few published works have targeted calibrating the bandwidth mismatch in the background mode.

Recent results: The contribution of 1/f noise in advanced technology has been verified by simulation. 1/f noise contributes more than thermal noise to the total noise power, and the 1/f corner frequency could be above 1 GHz. A new solution to reduce 1/f noise at high speed is being explored and implemented. Additionally, the model of a hierarchical TI-ADC has been built. A background calibration algorithm has been verified and implemented to calibrate the bandwidth mismatch at the Verilog-A level.