Mixed-signal circuits and data converters Research goal: Analog-to-digital converters (ADCs) are essential in mixed-signal integrated circuits. As the processing speed increases, single-channel ADCs will meet a fundamental limit in the trade-off between speed, resolution, and power. Using time-interleaved (TI) architectures is attractive when the sampling rate is above several GHz. In most cases, the TI architectural choices have been justified based on heuristics and validated through extensive simulations. This can be time-consuming, error-prone, and offer limited understanding of the choices or alternate options. One of the goal of this project is to propose a systematic architecture design model which is applicable to multiple interleaved architectures to quantitatively assesses architectural trade-offs and their impact to power consumption. Additionally, a sensitivity analysis of the impact on dynamic performance from some of the interleaving mismatches is also investigated to guide calibration algorithms' choices.
Gap in the SotA: The interleaving artifacts of direct sampling TI architectures have been studied [1][2], but a power consumption analysis is missing or incomplete. [3] assesses the power consumption of direct sampling but not for the hierarchical architectures. While [4] discusses the bandwidth implications of hierarchical architectures, it does not include the power consumption analysis.
Recent results: We propose a new methodology to analyze different architecture choices of high-speed, medium-resolution hierarchical TI-ADC architectures based on power consumption and performance sensitivity to interlaving mismatches. The proposed mathematical models have been compared against transistor-level and behavioral-level simulations. The best architectures under various specifications can be obtained based on this methodology. The new methodology has been developed for TI-ADCs for wireless communication systems, but it can be extended with minor modifications to lower resolution/higher sample rate TI-ADCs such as those used in wireline communication systems. Moreover, with the experience of the TI architecture design, a high-speed medium-resolution TI-ADC is being designed, including high-linearity buffers.
