Hardware-efficient AI and ML Research Goal
The slowing of Moore’s law has diminished the performance gains traditionally achieved through transistor scaling, prompting the search for alternative approaches. One promising direction is 3D integration, which offers new design freedoms beyond conventional 2D layouts. This research investigates vertically-integrated logic fabrics, where programmable logic, interconnect, and configuration layers are co-designed in stacked structures. The objective is to leverage these additional degrees of freedom to improve flexibility, scalability, and efficiency, while addressing critical metrics such as area, power, and timing. Rather than adapting existing 2D architectures, this work aims to design compute architectures from the ground up to fully exploit the potential of 3D integration.
Gap in the State of the Art
Current reconfigurable architectures, such as FPGAs and CGRAs, are fundamentally optimized for 2D layouts. Simply stacking these designs in 3D leads to suboptimal performance due to inherent limitations in interconnect density, routing complexity, and thermal management. While 3D integration has been explored, systematic architectural innovation for 3D programmable fabrics remains scarce.
