Carbon-aware Design Space Exploration for AI Accelerators

Jiacong Sun , Georges Gielen and Marian Verhelst Hardware-efficient AI and ML
  • Research Goals: Current AI hardware optimization primarily focuses on performance improvement while overlooking environmental impacts. The AI industry's computational demands are doubling approximately every 100 days, creating an urgent need for quantitative evaluation and optimization of Greenhouse Gas (GHG) emissions from both hardware and software perspectives. This project aims to evaluate the GHG emissions of AI accelerators and develop design methodologies to reduce their environmental impact.
  • Gap in the State of the Art: Current research on accelerator optimization predominantly focuses on performance metrics. While some GHG modeling studies exist, they primarily target commercial products or general CPU/GPU platforms. No existing work has thoroughly examined accelerator design or architectural implications when considering GHG emissions as an evaluation metric. This knowledge gap prevents accelerator designers from understanding the potential environmental impacts of their design decisions.
  • Results: This project introduces GHG evaluation into the existing performance-oriented modeling framework (ZigZag). Additionally, we developed an intuitive evaluation method to visualize hardware optimization benefits from both performance and GHG perspectives. Through multiple experiments conducted on this platform, our results demonstrate that carbon-optimal choices often differ from performance-optimal choices, highlighting the need for future co-optimization strategies that consider both metrics simultaneously.
Get in touch
Jiacong Sun
Phd student
Georges Gielen
Academic staff
Marian Verhelst
Academic staff
Visualization of Power Source Dependencies in Hardware Selection
Visualization of Power Source Dependencies in Hardware Selection

Other research topics in Hardware-efficient AI and ML

Anda: Unlocking Efficient LLM Inference with a Variable-Length Grouped Activation Data Format
Hardware-efficient AI and ML
Man Shi, Arne Symons, Robin Geens, and Chao Fang | Marian Verhelst
Massive parallelism for combinatorial optimisation problems
Hardware-efficient AI and ML
Toon Bettens and Sofie De Weer | Wim Dehaene and Marian Verhelst
Decoupled Control Flow and Memory Orchestration in the Vortex GPGPU
Hardware-efficient AI and ML
Giuseppe Sarda | Marian Verhelst
Automated Causal CNN Scheduling Optimizer for Real-Time Edge Accelerators
Hardware-efficient AI and ML
Jun Yin | Marian Verhelst
A Scalable Heterogenous Multi-accelerator Platform for AI and ML
Hardware-efficient AI and ML
Ryan Antonio | Marian Verhelst
BitWave: Exploiting Column-Based Bit-Level Sparsity for Deep Learning Acceleration
Hardware-efficient AI and ML
Man Shi | Marian Verhelst
Uncertainty-Aware Design Space Exploration for AI Accelerators
Hardware-efficient AI and ML
Jiacong Sun | Georges Gielen and Marian Verhelst
Integer GEMM Accelerator for SNAX
Hardware-efficient AI and ML
Xiaoling Yi | Marian Verhelst
Improving GPGPU micro architecture for future AI workloads
Hardware-efficient AI and ML
Giuseppe Sarda | Marian Verhelst
SRAM based digital in memory compute macro in 16nm
Hardware-efficient AI and ML
Weijie Jiang | Wim Dehaene
Scalable large array nanopore readouts for proteomics and next-generation sequencing
Analog and power management circuits, Hardware-efficient AI and ML, Biomedical circuits and sensor interfaces
Sander Crols | Filip Tavernier and Marian Verhelst
Hardware-algorithm Co-design and Accelerator Architecture Exploration for hybrid DNN and DSP Workloads
Hardware-efficient AI and ML
Jun Yin | Marian Verhelst
Design space exploration of in-memory computing DNN accelerators
Hardware-efficient AI and ML
Pouya Houshmand and Jiacong Sun | Marian Verhelst
Multi-core architecture exploration for layer-fused deep learning acceleration
Hardware-efficient AI and ML
Arne Symons | Marian Verhelst
HW-algorithm co-design for Bayesian inference of probabilistic machine learning
Ultra-low power digital SoCs and memories, Hardware-efficient AI and ML
Shirui Zhao | Marian Verhelst
Design space exploration for machine learning acceleration
Hardware-efficient AI and ML
Arne Symons | Marian Verhelst
Efficient execution of irregular data flow graphs: Hardware/software co-optimization for probabilistic AI and sparse triangular systems
Hardware-efficient AI and ML
Marian Verhelst
Cross-layer Dataflow Optimization for DNN Accelerators Exploiting Multi-bank Memories
Hardware-efficient AI and ML
Man Shi | Marian Verhelst
Enabling Fast Exploration of the Depth-first Scheduling Space for DNN Accelerators
Hardware-efficient AI and ML
Arne Symons | Marian Verhelst
Optimized deployment of AI algorithms on rapidly-changing heterogeneous multi-core compute platforms
Ultra-low power digital SoCs and memories, Hardware-efficient AI and ML
Josse Van Delm | Marian Verhelst
High-throughput high-efficiency SRAM for neural networks
Ultra-low power digital SoCs and memories, Hardware-efficient AI and ML
Wim Dehaene and Marian Verhelst
Heterogeneous Multi-core System-on-Chips for Ultra Low Power Machine Learning Application at the Edge
Hardware-efficient AI and ML
Pouya Houshmand, Giuseppe Sarda, and Ryan Antonio | Marian Verhelst

Want to work with us?

Get in touch or discover the way we can collaborate.
Contact us
Discover how we can collaborate