Design space exploration of in-memory computing DNN accelerators

Research goals: In recent years, in-memory computing (IMC) has emerged as a promising alternative to PE-based accelerators, by performing the MAC operations near/in the memory cells directly. This allows to greatly reduce access overheads and enables massive parallelization opportunities, with potential orders of magnitude improvements in energy efficiency and throughput. However these architectures suffer from lack of dataflow flexibility and thus potentially low utilization. The research focuses on exploring the algorithm-hardware design space for in-memory computing DNN accelerators.

Gap in the SotA: Recent IMC designs published in the literature are focused on analog IMC (AIMC), where the computation is carried out in the analog domain. While this approach ensures extreme energy efficiencies and massive parallelization, the analog nature of the computation compromises the output accuracy and the rigid structure of the computation's dataflow limits the spatial mapping possibilities. Digital in memory computing (DIMC) is lately gaining more interest as a valid alternative, thanks to its noise-free computation and more flexible spatial mapping possibilities, trading off added flexibility and accurate computation for less energy efficiency. Research work is needed to explore the design space of DIMC designs versus AIMC ones.

Research project: The ZigZag design space exploration tool is expanded with models for AIMC and DIMC specific building blocks. This allows to assess the impact of these technologies and related hardware parameters at the system level.