Ultra-low power digital SoCs and memories The demand for ultra-low power applications has significantly grown, powered by the emergence of IoT. In digital integrated circuits, ultra-low voltage operation has become a very promising method for this purpose. However, it aggravates the sensitivity to intra-die variations, especially in advanced nm scale technologies. Consequently, conventional design flows need to manage large design margins to ensure an acceptable yield, which can partially annihilate the technology scaling profit.
Current SotA: An extended mechanism to trim this additional margin is based on the insertion of in-situ timing monitoring, operating the chip at or near the Point of First Failure (PoFF). However, the substantial timing spread complicates the critical path identification, since nominally sub-critical paths may become critical when variation is considered. Missing the placement of a transition detector on a critical path entails the risk of false positives, where errors occur but the in-situ technique indicates an error-free operation, thus further scaling the voltage/frequency. Currently, there is no systematic methodology to identify the optimal location and number of transition detectors. This hinders the application of in-situ timing monitoring techniques beyond the research field, such as in industry. Here, the systems are typically designed using a 4 sigma production yield, ie 63.34 ppm.
Our approach: This research delves into in-situ warning detection, where potential timing errors are detected before they occur and corrupt the system. The information of the warning detectors is then used in a DVFS to operate the circuit near the PoFF. To achieve this, we designed a novel methodology that improves the energy-efficiency binomial eliminating the unnecessary margins and guaranteeing the conventional production yield. This methodology inserts in-situ warning detection on an automated and compatible way with a conventional industrial design flow. Main field of application is the design of generic DSP blocks. Tested on a 22-nm CMOS DSP block, results show that with this methodology we can safely recover more than 95% of the conventional energy design margin, improving the energy efficiency by 30-40% with a low area overhead.
