SRAM Macro Design

In deep submicron systems, voltage scaling in the digital processing unit is crucial for ultra low energy applications. This results in near-threshold operation, where increased variability is observed. For the logic portion, there are techniques to cope with this variation using timing error dectection and correction (EDAC). For memories however, current implementations require large margins to ensure correct operation of all cells. This work focusses on reducing these margins with two designs: (1) monitoring of cell stability, (2) in-situ EDAC using an error correction code.

In both designs, the memory is partitioned into local blocks (LB) to reduce the parasitic capacitance on long bit- and wordlines, ensuring fast access and low dynamic energy. This LB architecture also enables leakage reduction. Since activity is situated in one LB, all other LBs can be placed in deep sleep, with a reduced supply and power-gated periphery. Since LBs are small and access times are relatively long, it is feasible to take a single LB out of retention within a fraction of an access cycle.

The first work focusses on cell leakage in retention. To reduce hold margin and thus the retention voltage, we use the LB structure even further. The hold margin is measured for each LB, which contains 32 monitor cells, and is smaller for a lower number of cells. Then, this LB is tuned accordingly by selecting one of the two bulk biases.

The prototype is a 6.6MHz SRAM of 1Mbit, comprising 256 LBs, each with 128 words of 32 bits.

With in-situ EDAC, the second work can not only detect hold errors, but also timing errors. If a bit of a word arrives too late, it is flagged by the EDAC system. Then, an interrupt can be triggered to modify the timing re-read the memory. If the error still occurs, it is flagged as a hold error. The prototype of this memory is currently in the measurement phase.