Clara Nieto Taladriz Moreno

> In-situ timing detection

> Ultra-Low Energy Digital CMOS

> Near-threshold CMOS

Clara Nieto Taladriz Moreno
Clara Nieto Taladriz Moreno
Phd student

Current research topic

Career overview

Clara Nieto Taladriz was born in Madrid, Spain, 1994.

In 2016, she received the B. Sc. degree in electrical engineering from the Universidad Politécnica de Madrid (UPM), Spain.

In 2018, she received the M.Sc. degree in Telecommunication Engineering from the Universidad Politécnica de Madrid (UPM), Spain. She completed the second year of the M.Sc. degree as an exchange student in Katholieke Universiteit Leuven (KU Leuven), Belgium. The subject of her master thesis was: "Towards Efficient and self-sustaining BLE Mesh: Design and Implementation of an Autonomous Network Joining Algorithm".

Later in 2018, she became a KU Leuven Ph.D. student at ESAT-MICAS, under the guidance of Prof. Wim Dehaene, with a research interest in in-situ timing detection strategies for ultra-energy-efficiency and low-voltage digital circuit operation. 


Automated In-Situ Monitoring for Variability-Resilient and Energy-Efficient Digital Circuits Demonstrated on a Viterbi Decoder in 22-nm CMOS Clara Nieto Taladriz Moreno and Wim Dehaene · Article · Jun 26. 2023 IEEE Transactions On Very Large Scale Integration (Vlsi) Systems; 2023; Vol. 31; iss. 9; pp.
Dealing with the Energy Versus Performance Tradeoff in Future CMOS Digital Circuit Design Wim Dehaene, Roel Uytterhoeven, Clara Nieto Taladriz Moreno, and Bob Vanhoof · Book Chapter · Mar 1. 2020 NANO-CHIPS 2030; 2020; pp. 89 - 115
Towards Efficient BLE Mesh: Design of an Autonomous Network Joining Algorithm Clara Nieto Taladriz Moreno, Yuri Murillo Mange, and Sofie Pollin · Conference Proceeding · Nov 12. 2018 2018 IEEE Symposium on Communications and Vehicular Technology (SCVT'18); 2018; Vol. abs/1907.08419; pp.


Digital Design of Integrated Circuits