Ultra-low power digital SoCs and memories Context: In previous work (see Automated in-situ monitoring for variability resilient and energy efficient digital ciruits) we have delved into in-situ timing monitoring techniques to operate digital circuits at low voltage with the aim of addressing the high demand of ultra-low power applications in the industry. Our previous work proposes a systematic methodology to ensure production yield while safely recovering more than 95% of the conventional energy design margin, improving the energy efficiency by 30-40%.
Limitations: The proposed technique becomes especially successful in devices with basic functions of many signal-processing algorithms, such as DSP blocks. That is, in devices where the entire hardware is involved in the execution of its task and the activity is mostly constant. However, more complex and general-purpose devices, such as microcontrollers, can be adapted to a wide variety of applications by software. Therefore, running different software can alter both the activity in the circuit and the hardware parts involved. This dependency on activity uncertainty can affect the robustness of in-situ timing monitoring techniques, hindering its application beyond the research field, such as in industry.
Our proposal: This work differentiates two planes in the design of the in-situ warning detection techniques. Those are the physical location of the monitor within the path and the clock moment at which monitors are observed. The combination of both planes becomes a trade-off between activity detected in the circuit and design margins. In this work, we seek the balance between both planes to deploy an in-situ warning detection technique that guarantees production yield independent of activity uncertainty and that maximizes the elimination of unnecessary margins. We do this on a 28nm CMOS RISC-V microprocessor with an ultra-low area overhead of less than 2%.
