High-resolution neurostimulator ICs for the Visual Cortex

Blindness has a severe impact on quality of life. In a significant part of the cases, millions worldwide, blindness is caused by disorders which irreversibly damage the retina (retinitis pigmentosa, age-related macular degeneration) or the optical nerve (glaucoma). Electrical stimulation of the unaffected visual cortex has been shown to successfully elicit visual percepts in blind persons, proving the viability of a visual prosthesis to restore vision for these currently untreatable cases.

This work contributes the integrated circuit design to an interdisciplinary research project which develops a visual prosthesis targeting the visual primary cortex. Visual prostheses require a high-channel-count stimulator (>1000) to provoke images with sufficient resolution for common tasks such as reading or recognizing faces. The design of such a stimulator faces three main challenges. First, the high channel-count dictates an integrated solution which minimizes area per channel. Second, the stimulator must ensure long-term safety, which means that it must deliver biphasic, charge balanced current pulses with no more than 100nA DC error current. The resulting accuracy is costly in terms of area due to matching constraints.
Third, by miniaturizing the electrodes to achieve local, high-resolution stimulation, the impedance of the electrodes increases and requires electrode drivers to sustain over 10V. Employing high-voltage circuitry incurs a significant area cost.

To face these challenges, a novel, digital time-domain calibration strategy was devised which allows safe stimulation while maintaining state-of-the-art area/channel. A 16-channel prototype was fabricated and successfully validated in a low-voltage CMOS technology, yet achieving 10.4V output swing and a low 145µm x 97µm area per channel, comparable with state-of-the-art low-voltage simulators.

Work is ongoing to extend this prototype to a full 256-channel SoC with integrated microcontroller. Owing to the choice for a modern low-voltage process, digital control blocks scale well. Furthermore, a secondary passive charge balancing method is being investigated as a failsafe mechanism. This requires integration of a high-voltage bidirectional switch in the low-voltage CMOS process.