Computer-aided hardware design and test Research goals: CMOS based Ising accelerators have emerged as a promising approach for solving combinatorial optimization problems (COPs). However, existing designs mostly optimize the computational logic in isolation and pay little attention to end to end system performance, including memory accesses and data transfers. This work aims to develop an analytical emulator that evaluates hardware system level performance across a broad range of Ising applications.
Gap in the state of the art: Existing design space exploration frameworks primarily target AI and machine learning workloads. None, to our knowledge, are tailored to Ising based optimization. Current Ising accelerator designs focus on optimizing the computation units only, while leaving memory, communication, and system integration largely unexplored, even though these components can exhibit different scaling trends than the core logic.
Result: Our experiments show that peak system level performance scales differently from logic only performance, with a gap of at least 15x between the two. Evaluations across diverse benchmarks further reveal that the optimal hardware architecture chouces depend strongly on the targeted application, underscoring the need for application aware exploration and system-level design of Ising accelerators.
