Machine Learning-based Automated Analog Integrated Circuit Sizing

Research goal:
Analog/mixed-signal circuits are an essential part of any electronic system that requires interaction with the outside physical world. These circuits find applications in various fields such as the internet of things (IoT), biomedical technology, imaging, and telecommunication systems. Although digital circuits form the backbone of most electronic systems, the analog component, despite occupying a relatively small chip area, remains a significant bottleneck in design efforts. This is primarily due to the lack of efficient and widely embraced automation tools.

In the analog design cycle, circuit sizing poses a significant challenge due to its time-consuming and labor-intensive nature, primarily attributed to the high dimensionality of the design space. Over the past decades, various simulation-based methods have been proposed to tackle this issue, leveraging black-box optimization tools such as Genetic Algorithms (GA) and Bayesian Optimization (BO). In recent years, there has been a notable shift towards automation in analog circuit sizing, with the adoption of Reinforcement Learning (RL) algorithms, showcasing improved sample efficiency and reduced time consumption. Specifically, actor-critic RL methods like Deep Deterministic Policy Gradients (DDPG) have demonstrated efficiency in the sizing of analog circuits.

Research approach:
In our research, we have focused on applying state-of-the-art Reinforcement Learning algorithms for sizing analog circuits. There are various challenges in this domain, most of which are related to the curse of dimensionality in design and the problem definition. Among these challenges are the following: 1) which multi-objective optimization approach to choose for the reward definition of the RL framework, 2) how to formulate the state and action space, 3) how to handle PVT variations, 4) how to partition large circuits into sub-blocks and find proper specifications for each sub-block, 5) how to size complex circuits consisting of multiple sub-blocks simultaneously,  6) how to find the constraints on matching and symmetry and decide for the number of optimization variables in each circuit, and 7) how to learn from existing designs and transfer knowledge for sizing other designs.

So far, we have developed a sample-efficient reinforcement learning framework that is able to size simple and complex circuits with higher speed than previous RL methods used in this field, in terms of both runtime and simulation count. We have used our method to size multiple circuits in the predictive 45nm technology. Furthermore, we developed methods to handle the circuit sizing under PVT variations and in more recent technologies.