Research challenges
To enable the efficient and correct design of future generations of complex analog, mixed-signal and RF integrated circuits in industry, several challenges need to be solved in the coming years, mainly focusing on further automating the design and the test development, but also accurately modeling emerging phenomena and technologies. Researchers at MICAS actively strive to work on the following challenges for the next 5 years.
AI/machine learning for analog circuit and layout synthesis
Despite the large progress in analog CAD methods over the past decades, the design of analog/mixed-signal ICs in industry is still largely done manually by designers, resulting in long and error-prone design cycles. MICAS has a long and renowned research tradition in developing CAD algorithms and methodologies to address this. Major weakness of today’s optimization-based methods, however, is the need for design heuristics and constraints to be entered explicitly by designers in order to handle the humongous solution space. The emergence of machine learning and AI offers avenues to address this problem. MICAS will carry out research to develop novel machine learning algorithms that learn and exploit the design expertise and constraints from existing completed designs and layouts, without designer in the loop, to automatically generate the circuit design and layout. Also more formal methods for analog design verification are being investigated.
Advanced models and methods for analog/mixed-signal test analysis and test generation
Safety-critical applications like automotive require test escape rates well below the 10 ppb level for their integrated circuits, ultimately delivering zero defective ICs. For a decade now and starting from above the ppm level, MICAS has been working towards this goal with significant progress. Yet, in the light of the hard-to-detect latent defects, sophisticated methods from advanced statistics and machine learning are being explored to further increase the overall defect coverage and to detect outliers that may have latent defects. In combination with proper defect modeling and design-for-test methods, including real-time online monitoring, this research will also focus on methods for fast and highly automated analog test program generation, aiming to reduce the test development time while at the same time increasing the effectiveness and test quality.
Modeling of quantum devices for efficient quantum computer simulations
Quantum computing promises to cause a revolution in computation. At this moment, research is going on to develop qubits with good scalability potential and long decoherence times, with spin qubits and superconducting qubits being main contenders. Since classical electronics are needed to control and read out the qubits, proper modeling and simulation tools are required for the co-design of the qubits together with their associated electronics. As the principles governing the behavior of the classical circuits and the quantum devices are different, this presents a unique challenge in terms of the simulation, design and optimization of the joint system. In collaboration with imec, research is carried out towards such accurate and efficient modeling and optimization.
Modeling and mitigation of time-dependent phenomena in advanced CMOS
Advanced scaling and the introduction of new materials in CMOS technologies impact the reliability of integrated circuits. Throughout the time of operation, several degradation mechanisms can cause a significant change of the transistor parameters and therefore of the IC performance and functioning. MICAS has a long tradition in modeling, simulating and mitigating such phenomena. While in large-area MOSFETs aging appears deterministic, in small-area devices it is stochastic and convoluted with random telegraph noise. Detailed models for the time-dependent aging and related stochastic random variability are developed as a function of major parameters such as device biasing and sizing; these models are always validated against measurements. The models are then used to guide designers towards reliable design and to develop mitigation methods to counter any growing degradation on chip.
