Weijie Jiang

  • Mixed signal design
  • SRAM design
  • In-memory-compute
Weijie Jiang
Weijie Jiang
Phd student
Ultra-low power digital SoCs and memories
0484338438
weijie.jiang@esat.kuleuven.be
Wim Dehaene
Or meet the full MICAS team

Current research topic

Career overview

  • 2014-2018, Shanghai Jiao Tong University, bachlor in microelectronics. 
  • 2018-2020, ESAT, KU Leuven, EE chip design division. 
  • 2020-now, MICAS, KU Leuven, low power SRAM and digital circuit. 

Publications

A 16nm 128kB high-density fully digital In Memory Compute macro with reverse SRAM pre-charge achieving 0.36TOPs/mm2, 256kB/mm2 and 23. 8TOPs/W Weijie Jiang, Pouya Houshmand, Marian Verhelst, and wim Dehaene · Conference Proceeding · Jan 1. 2023 ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC); 2023; pp. 409 - 412

Teaching

TA of Design of Digital Integrated Circuit