Shirui Zhao

Shirui Zhao

Shirui Zhao

Phd student

Hardware-efficient AI and ML

shirui.zhao@esat.kuleuven.be

Marian Verhelst

Or meet the full MICAS team

Current research topic

HW-algorithm co-design for Bayesian inference of probabilistic machine learning - Marian Verhelst

Publications

DPU: DAG Processing Unit for Irregular Graphs With Precision-Scalable Posit Arithmetic in 28 nm Nimish Shirishbhai Shah, Laura Isabel Galindez Olascoaga, Shirui Zhao, Wannes Meert, and Marian Verhelst · Article · Aug 1. 2022 IEEE Journal Of Solid-State Circuits; 2022; Vol. 57; iss. 8; pp. 1 - 11

A 703.4-GOPs/W Binary SegNet Processor With Computing-Near-Memory Architecture for Road Detection Haoran Lyu, Fengwei An, Shirui Zhao, Wei Mao, and Hao Yu · Article · Apr 1. 2022 IEEE Design & Test; 2022; Vol. 39; iss. 2; pp. 74 - 83

Discrete Samplers for Approximate Inference in Probabilistic Machine learning Shirui Zhao, Nimish Shah, Wannes Meert, and Marian Verhelst · Conference Proceeding · Jan 1. 2022 Design, Automation and Test in Europe Conference and Exhibition (DATE), 2022; 2022; pp. 1221 - 1226

PIU: A 248GOPS/W Stream-Based Processor for Irregular Probabilistic Inference Networks Using Precision-Scalable Posit Arithmetic in 28nm Nimish Shah, Laura Isabel Galindez Olascoaga, Shirui Zhao, Wannes Meert, and Marian Verhelst · Conference Proceeding · Jan 1. 2021 Proceedings of 2021 IEEE International Solid- State Circuits Conference (ISSCC); 2021; Vol. 64; pp. 1 - 3

A 307-fps 351.7-GOPs/W Deep Learning FPGA Accelerator for Real-time Scene Text Recognition Shirui Zhao, Fengwei An, and Hao Yu · Conference Proceeding · Jan 1. 2019 2019 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (ICFPT 2019); 2019; pp. 263 - 266