Sankhya Bhattacharya

Design for Testability and Chip Reliability

Sankhya Bhattacharya

Phd student

Computer-aided hardware design and test

0496975564

sankhya.bhattacharya@esat.kuleuven.be

Georges Gielen

Or meet the full MICAS team

Current research topic

Testing and design for testability of latent defects in mixed-signal integrated circuits - Georges Gielen

Career overview

2024 - Present: Currently pursuing PhD on " Automated machine-learning-based test generation for analog/mixed-signal integrated circuits" under Prof.Georges Gielen

2018-2024: Worked as Product Development Engineer on ATE based Test Development for FPGA and mixed signal products at Intel Corporation, India. Prior to joining Intel he worked as a Product Test Engineer for Memory solutions at Micron and Qualcomm.

He holds a M.S in System Science from NTHU,Hsinchu,Taiwan and a B.E in Electronics from MAHE,Manipal,India

Publications

Hybrid AI-Optimization Method for Latent Defect Detection Through Test Transistor Insertion in Analog Circuits Sankhya Bhattacharya and Georges Gielen · Conference Proceeding · Jul 29. 2025 2025 21st International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuits Design (SMACD); 2025