Kaichang Chen

  • Computer-Aided Design of Integrated Circuits and Systems
  • Mixed-signal and Analogue Circuits
Kaichang Chen
Kaichang Chen
Phd student
Computer-aided hardware design and test
+32 484412923
kaichang.chen@esat.kuleuven.be
Georges Gielen
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Current research topic

Career overview

Kaichang Chen was born in Shaanxi, China, in 1999.

In 2021, he received the B. Sc. degree in Electronic Informational Engineering from the Beijing Institute of Technology (BIT), China.

In 2022, he received the M. Sc. degree in Analogue and Digital Integrated Circuits Design with Distinction from Imperial College London, U.K. The subject of his master's thesis is: "A Wide-Input Range ISFET Readout Circuit with Low-Power Linearity Enhancement", in collaboration with Centre for Bio-Inspired Technology, U.K.

He is currently working toward the Ph.D. degree in electrical engineering here, under the supervision of Prof. Georges Gielen, with a research interest in Machine Learning/AI-based Automated Layout Synthesis of Analogue and Mixed-signal Integrated Circuits.

 

Publications

Self-learning and transfer across topologies of contraints for analog/mixed-signal circuit layout synthesis Kaichang Chen and Georges Gielen · Conference Proceeding · Mar 28. 2024 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE); 2024; pp. 1 - 6
A Wide-Range ISFET Readout Circuit with Low-Power Linearity Enhancement Kaichang Chen, Prateek Tripathi, Nicolas Moser, and Pantelis Georgiou · Conference Proceeding · Jan 1. 2023 2023 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, ISCAS; 2023; pp.

Teaching

Exercise Session: Analog Filter Design [Analog and Mixed-Signal Electronics for Signal Processing 2023-2024]

Lab Session: Analog Circuit Layout Automation [Computer-Aided IC design 2024]