Kaichang Chen was born in Shaanxi, China, in 1999.
In 2021, he received the B. Sc. degree in Electronic Informational Engineering from the Beijing Institute of Technology (BIT), China.
In 2022, he received the M. Sc. degree in Analogue and Digital Integrated Circuits Design with Distinction from Imperial College London, U.K. The subject of his master's thesis is: "A Wide-Input Range ISFET Readout Circuit with Low-Power Linearity Enhancement", in collaboration with Centre for Bio-Inspired Technology, U.K.
He is currently working toward the Ph.D. degree in electrical engineering here, under the supervision of Prof. Georges Gielen, with a research interest in Machine Learning/AI-based Automated Layout Synthesis of Analogue and Mixed-signal Integrated Circuits.
Exercise Session: Analog Filter Design [Analog and Mixed-Signal Electronics for Signal Processing 2023-2024]
Lab Session: Analog Circuit Layout Automation [Computer-Aided IC design 2024]