The rapidly increasing heterogeneity in algorithms for artificial intelligence requires new hardware that can perform the different types of calculations at low latency and high energy-efficiency. Yet, some machine learning kernels can be executed most efficiently on analog AI coprocessor, while other kernels require more accuracy or have less parallelism, making them better suited for a digital coprocessor. The solution we are proposing in our new Diana chip combines the best of both worlds on one compact chip to always performs calculations in the most energy-efficient way.
DIANA is a low-power NN processing SoC, comprising a precision-scalable digital NN accelerator and an AiMC core, controlled by a RISC-V host processor for end-to-end inference at the Edge.
This SoC includes innovations in :
a.) its 16×16 digital NN core with flexible dataflow for fully connected and high-precision CONV layer execution,
b.) its 1152×512 AiMC core with SIMD digital postprocessing and support for output unrolling for improving array utilization, and
c.) a shared memory system supporting efficient layer-fused execution schedules, controlled by the RISC-V.
This allows simultaneous execution of subsequent layers across the digital and analog cores, assigning high-precision layers and layers with limited AiMC utilization (e.g. FC layers and layers with low channel count) to the digital core, and all other intermediate layers to the AiMC core.
The chip is designed by the team of Prof. Verhelst.
© Picture - imec
