High-speed wireline communication systems place increasingly stringent demands on analog-to-digital converters (ADCs) in terms of sampling rate, bandwidth, and energy efficiency. With continuously increasing data rates and channel loss, modern wireline receivers rely heavily on large-scale digital signal processing, such as decision feedback equalization (DFE), to maintain link performance. The implementation of such complex DSP blocks strongly benefits from advanced CMOS technologies, making it attractive to also realize the front-end ADC in the same advanced process node.
In this context, time-domain ADCs have attracted growing interest due to their strong compatibility with technology scaling. By representing analog signals in the time domain and leveraging fast inverter-based and dynamic circuits, time-domain techniques can effectively exploit the improved switching speed offered by advanced CMOS technologies, making them particularly promising for ultra-high-speed wireline applications.
The aim of this research is to explore time-domain ADC architectures tailored for wireline communication systems. The seminar will introduce ADC requirements in modern wireline receivers, provide an intuitive overview of voltage-domain and time-domain signal conversion, and conclude with circuit-level examples and key design considerations.
9/1/2026 11:00 - 12:00
ESAT Aula L
