Deeply implantable neural stimulation calls for architectural solutions that are small, efficient and flexible, and can stimulate many electrodes. To this end, the use of a pulsed (chopped) voltage stimulator, implemented using a low-complexity switch network with fully adaptive real-time control is proposed. The fully-integrated control architecture guarantees current waveform reconstruction and charge balancing by continuously monitoring the charge delivered to the electrode, thus offering robustness towards power-supply voltage and electrode impedance variations. The architecture has a high thermal efficiency across the entire output operating range. The output waveform is generated in charge samples (slices) of controlled amount; by distributing these slices properly, the desired arbitrary stimulation waveform is constructed. A voltage monitoring circuit is used to apply active charge balancing; the duration of the balancing phase is adjusted by varying the number of samples. The feasibility of the architecture is demonstrated with a chip prototype manufactured in a 180 nm, 1.8 V/5 V CMOS node, and has an area of only 0.027 mm^2 per non-multiplexed stimulator channel. Across the entire output operating range, experimental validation of the prototype demonstrates a thermal efficiency that is up to 40% better than previously published implementations. The results show that this architecture is a viable solution for the next generation of systems for neuromodulation and closed-loop neural monitoring.
8/11/2024 11:00 - 12:00
ESAT B91.200
