As the complexity and performance demands of digital systems continue to escalate, traditional RTL-based design methodologies often struggle to keep pace with modern development cycles. Stratus High-Level Synthesis (HLS) offers a transformative approach by enabling designers to work at a higher level of abstraction using C, C++, or SystemC, significantly reducing design time. This seminar introduces Stratus HLS, emphasizing its relevance and applicability to cutting-edge digital design prototyping. We will explore its capabilities for architectural exploration and automatic RTL generation, highlighting how SystemC can be leveraged for more accurate modeling and simulation in early design stages.
6/6/2025 11:00 - 12:00
ESAT B91.200
