Event - 28 April 2025

PhD Defence : Ultra Low Voltage Variation Resilient Digital Circuit Design

Lectured by Clara Nieto Taladriz Moreno

What

The increasing demand for low-power devices in today’s industry drives this research, which aims to make digital circuits more energy-efficient while ensuring reliability. A key focus is the development and integration of in-situ timing detection—a technique that monitors and adjusts circuit operation in real time to operate the circuit at its optimal capabilities and reduce power consumption. These methods are rigorously tested on advanced silicon prototypes and designed to seamlessly integrate into standard manufacturing processes. This work contributes to the creation of smarter, more sustainable electronic devices.

When

28/4/2025 17:00 - 19:00

Where

Department of Electrical Engineering, Kasteelpark Arenberg 10, 3001 Heverlee, ESAT Aula C (B91.300)