The Internet of Things (IoT) has brought about a huge growth in connected smart devices. These devices are mostly battery operated, but have low operating speed requirements, which enables low energy operation. When looking at state of the art microcontroller implementations for these devices, the leakage energy budget of the memory is prominent. This work focuses on the leakage optimisation in memories to increase battery life of IoT devices.
In modern technologies, transistor variation is the main cause for high leakage, as the worst-case transistor determines the leakage profile for the entire memory. As a solution, this work uses the state of the art memory topology to divide this problem into smaller memories. Then, two transistor tuning knobs, body biasing and voltage scaling, are used on these smaller memories and the leakage is optimised for each individual smaller memory. However, individual tuning of these smaller memories requires some internal knowledge about these memories. Thus, the thesis shows two methods of monitoring: analog monitoring and digital monitoring. The latter option results in a lower total leakage level. Furthermore, more power can be saved by switching the small memories in sleep-mode when not in use.
These proposed techniques are validated in two prototype chips. The first prototype shows analog monitors and body bias compensation. As a result, the most prominent component in the leakage power budget is reduced with more than 50%. The second prototype shows a digital monitoring technique and voltage scaling compensation. This results in a 70% decrease of leakage power overall. When using the second prototype in an IoT application, it shows the lowest total power consumption compared to other state of the art memories.
1/2/2024 17:00 - 19:00
ESAT Aula C, B91.300
