This dissertation aimed to provide a holistic approach for accelerating machine learning applications and algorithms on resource- and battery-constrained embedded hardware devices at the (extreme) edge. This is driven by the exponential growth of IoT applications and the proliferation of (extreme) edge devices as more and more applications move down the cloud-edge continuum toward near-sensor processing. However, most machine learning models impose high complexity for computation and model storage, which is infeasible for the (extreme) edge devices to fulfill. Algorithmic innovation techniques such as model compression, efficient models, resource-aware model generation, etc., have proven to alleviate this bottleneck to a large extent. But general-purpose systems can seldom take advantage of these techniques and the implicit high parallelism opportunities the ML models expose. The solution is to build specialized hardware accelerators which are incredibly high-performant and energy-efficient for a specific application and algorithm. The drawback of this specialized hardware approach is the tendency to lag behind the rapid evolution of ML software (applications and algorithms). This is especially true in the case of the IoT paradigm, where new applications, algorithms, and data acquisition techniques are rapidly changing. At the same time, the fixed hardware puts a brake on the applications that can be deployed on (extreme) edge computing.
The overarching goal of this dissertation was to optimally trade off energy efficiency for flexibility to enable hardware platforms that can keep up with the evolving machine learning software for ML at the (extreme) edge. This was achieved through carefully co-designing hardware and algorithms, considering the relevant performance metrics. The first portion of the dissertation focused on the algorithms and the framework for exploiting the co-optimization opportunities available in the ML hardware-algorithm design space. The second part exploited the insights gained from the former to build highly energy-efficient hardware implementations for specialized applications. The final portion then moved up the vertical stack to integrate specialized single-core accelerators into heterogeneous multi-core systems-on-chip, showing its imbued flexibility. The dissertation fulfilled its journey from building specialized hardware accelerators to more flexible heterogeneous multi-core systems and proposed this as one of the optimal solutions for future (extreme) edge ML processors.
Defence starts at 16.30h.
2/5/2023 16:30 - 18:30
ESAT Aula R
