Since its invention in the late 1960s, Dynamic Random-Access Memory (DRAM) has powered everything from personal computers to mobile phones and servers. Over the years, it has become faster and more compact. However, with the rise of artificial intelligence (AI) and high-performance computing (HPC), traditional DRAM is struggling to keep up due to physical scaling limits and growing data transfer demands. This research addresses two key challenges: the slowdown in DRAM miniaturization below 20 nanometers and the “memory bottleneck” created by the high bandwidth demands of AI applications. Three innovative memory strategies are proposed:
• 2T0C-IGZO with Half-Voltage Precharge: Improves read speed and data reliability by using a lower precharge voltage. It achieves 10× fasterreads with drastically reduced energy and size requirements.
• Hybrid Sensing Architecture (HSA): Enables high-density, low-power memory arrays with fast access times (under 10ns), while remaining robustunder temperature and manufacturing variations.
• Ferroelectric RAM (FeRAM): Explores ferroelectric materials as a DRAM alternative. The study examines how capacitor size impacts speed,reliability, and resistance to write disturbances
Together, these techniques push memory performance to new levels, paving the way for energy-efficient and high-density solutions that meet the growing demands of modern AI and HPC systems.
9/1/2026 14:00 - 16:00
ESAT Aula R
