Plasmonic logic combines deep-subwavelength confinement with ultrafast propagation, making it attractive for dense, high-bandwidth on-chip computing. Its practical deployment, however, is limited by the electronic interface required to convert the output current of a plasmonic MSM detector into a reliable logic decision at very high data rates. This thesis investigates a compact, low-power CMOS detector-readout front end in an IMEC calibrated sub-3 nm PDK. The objective is to co-design the TIA, isolation stage, and four-way time-interleaved StrongARM decision path under post-layout parasitic constraints.
21/8/2026 17:00 - 19:00
Aula van de Tweede Hoofdwet, 01.02, Kasteelpark Arenberg 41, 3001 Heverlee
