Over the past decade, Deep Learning (DL) has revolutionized the field of Artificial Intelligence (AI), being widely adopted in diverse domains, such as computer vision, natural language processing, healthcare, manufacturing, robotics, etc. To further liberate DL’s productivity and promote exciting new applications, faster and more efficient DL model execution is required, especially in resource-constrained scenarios such as mobile and IoT devices. Various DL accelerators are built for this purpose. DL acceleration involves multi-level design considerations (e.g., model, hardware, and mapping), with each level presenting a large design space. This, however, makes it challenging to jump out of the sub-optimal, ad-hoc design paradigm, as it is hard to efficiently explore the vast design space through the traditional slow and costly IC implementation. This thesis tackles this challenge by developing a series of fast and novel Design Space Exploration (DSE) methodologies, benchmarks, and frameworks, aiming to help designers systematically understand the design space of DL accelerators at different abstraction levels and develop better DL acceleration systems.
24/8/2023 16:30 - 18:30
Aula van de Tweede Hoofdwet, 01.02, Kasteelpark Arenberg 41, 3001 Heverlee
