Event - 21 September 2023

PhD Defence: Carl D'heer

THz Circuit Design for High-Speed Telecommunication


This thesis focuses on the development of innovative architectural and circuit-level solutions to enable high-speed (sub-)THz communication in CMOS technologies. A comprehensive numerical model of high-speed links is developed to identify critical performance bottlenecks and provide system-level design guidelines for higher speed and efficiency communication systems. Based on the modeled trends, various transceiver architectures are analyzed for their feasibility. Nonlinear THz transmitters are discussed to enable high data rate transmission above the maximum frequency of the technology. A new transceiver architecture is proposed, which achieves high-speed operation at sub-THz frequencies with improved energy efficiency compared to conventional architectures. This transceiver relies on direct-digital (de)modulation, effectively performing complex modulation and demodulation without the need for high-performance, power-consuming data converters. The thesis also presents a practical design methodology with several circuit-level innovations to ensure efficient CMOS circuit implementation at high frequencies.

The proposed solutions are validated through the implementation of several integrated circuits or chips, and the realization of a complete high-speed sub-THz communication link.
(1) A nonlinear 390 GHz transmitter is designed, supporting 28 Gbps using a non-conventional modulation technique called BPOOK.
(2) A 135 GHz direct-digital modulation 16-QAM transmitter is presented, capable of generating 16-QAM signals up to 36 Gbps without the need for a high-speed multi-bit DAC or offline signal processing.
(3) A 135 GHz direct-digital demodulation 16-QAM receiver is proposed, demonstrating 16-QAM demodulation up to 32 Gbps directly to binary outputs, eliminating the need for a high-resolution ADC.
(4) A complete 16-QAM link operating at 135GHz is established over a wireless channel and a dielectric waveguide, achieving a maximum data rate of 32 Gbps with on-chip modulation and demodulation, without any offline digital signal processing, while achieving state-of-the-art energy efficiency. All designs were implemented in 28 nm bulk CMOS technology and validated through extensive measurements.


21/9/2023 17:00 - 19:00