High-speed Analog-to-Digital Converters (ADCs) perform an important function in the front end of communication systems. Due to process technologies’ limitations, medium resolution (8b to 14b) single-channel ADCs lose conversion efficiency for sampling rate greater than few GHz. Time-interleaved ADCs (TI-ADCs) sample at a higher rate by multiplexing N identical ADCs, called sub-ADCs. Ideally, a TI-ADC’s power consumption is N times the sub-ADC’s power. However, multiple non-idealities, such as mismatches between the sub-ADCs, interconnect parasitics, etc., introduce spurious spectral artifacts requiring overhead circuitry, calibration, and other mitigation techniques that consume additional power.
In this seminar, we will start from the architecture-level design. Different TI architectures will be compared under various specifications based on a model that includes many power consumption considerations. Then, followed by a design of a 32-GS/s TI-ADC front end as an example. Finally, one of the building blocks, the input buffer, will be introduced and improved under such a high-speed and high-linearity requirement.
6/12/2024 11:00 - 12:00
ESAT Aula R
