Wearable Augmented Reality (AR) devices are poised to create new AI-enabled user experiences. For this, AR devices will require running AI and ML algorithms, graphics pipelines, image and audio processing applications, and many more demanding workloads on platforms that are heavily constrained in area footprint and battery power. Enabling such high performance applications running on a tight power budget within a compact wearable form-factor, however, presents unique design challenges. As a result, custom silicon is one of the key innovations to enable these rich features in an energy and area efficient manner. In this talk, we will highlight the research directions of our team at Reality Labs, Meta, that address different aspects of these silicon design challenges, such as compute and memory innovations to overcome AR system-on-chip (SoC) resource limitations, and hybrid-bonding based 3D stacked architectures and 3D design methodologies for area- and energy-efficient on-device acceleration.
Speaker Bio :
H. Ekin Sumbul received his BS degree in Electronics Engineering from Sabanci University, Istanbul, Turkey in 2010, and his Ph.D. degree in Electrical and Computer Engineering (ECE) from Carnegie Mellon University, Pittsburgh, PA, USA in 2015. He worked as a research scientist at Intel Labs, Hillsboro, OR, USA in Circuits Research Lab from 2015 to 2020. Since 2020, Dr. Sumbul has been working at Reality Labs, Meta, Sunnyvale, CA, USA, as a research scientist. His current research interests lie in energy-efficient AI/ML accelerators and silicon innovations for Augmented Reality/Virtual Reality (AR/VR) devices. Dr. Sumbul has been an active member of the research community since 2010 by authoring multiple papers and patents, and by serving as TPC in various conferences and journals such as ESSERC, DAC, CICC, and JSCC. As of 2025, Dr. Sumbul is a Senior IEEE member.
4/4/2025 14:00 - 15:00
ESAT B91.200
