Noise, mismatch, and process variations have long been regarded as fundamental limitations in electronic systems. As CMOS technologies continue to scale, however, these non-idealities become increasingly difficult to suppress, making the realization of high-precision, deterministic data converters progressively more challenging and costly. Since noise and variability are inherent properties of physical systems, an alternative approach is to exploit their statistical properties to improve system-level performance.
This seminar explores how redundancy and statistical averaging can mitigate the effects of noise, mismatch, and timing uncertainty in modern data converters. By combining multiple imperfect measurements, stochastic architectures can achieve resolutions beyond the limits imposed by individual circuit elements while maintaining robust and scalable operation in deep-nanometer CMOS technologies.
The discussion covers both temporal and spatial forms of redundancy, highlighting how concepts traditionally associated with probability and statistics can be translated into practical circuit-design techniques. Examples drawn from stochastic analog-to-digital converters and coupled ring oscillator architectures illustrate how averaging across time, space, and distributed phase references can improve resolution, robustness, and efficiency.
The central message is simple: if noise cannot be avoided, the most effective strategy may be to use it in your favor.
26/6/2026 11:00 - 12:00
ESAT Aula L
