The execution of AI models on edge devices (i.e. smartphones, wearables, drones, IoT nodes) requires the careful co-design of dedicated hardware architectures and scheduling methods. Due to the scarce hardware resource availabilities on the edge – limited power budgets and silicon area – the goal is to maximally utilize the parallelism and/or caching possibilities of the hardware on target workloads. However, the design space to be explored is enormous and rapid exploration of the mapping (i.e. scheduling) and hardware space is required. Furthermore, the adoption of alternative computing paradigms in recent years, most notably in-memory computing (IMC), for edge AI acceleration further enlarges the design space to be explored.
28/1/2025 17:00 - 19:00
Aula Arenbergkasteel (01.07), Kasteelpark Arenberg 1, 3001 Heverlee
