Digital integrated circuits are conventionally designed with timing margins to tolerate variability in manufacturing, operation conditions and applications. These margins guarantee reliable operation against unfavorable combinations of process, voltage, temperature (PVT) and workload-dependent effects, but leave substantial wasted energy and performance potential in individual dies under standard operation. Lowering the supply voltage is among the most effective means to improve energy efficiency and recover these margins. However, achieving this reduction safely requires understanding how timing behavior varies, how it can be observed and/or predicted, and how and when the available information can be used to properly adapt the operating point.
This seminar examines timing variability from design-time analysis and sign-off guardbands to silicon characterization and monitoring techniques, highlighting the information provided and limitations associated with each examined approach. It then discusses the researched methodologies about statistical in-situ monitor characterization and ongoing work towards runtime adaptive per-die optimization combining prediction with observation to determine and validate the best operating point to reliably improve energy efficiency.
13/11/2026 11:00 - 12:00
ESAT Aula C
