Traditional 2D silicon scaling is hitting a wall. Power and area gains are shrinking, horizontal wires are consuming massive amounts of energy, and off-chip memory bandwidth remains a relentless bottleneck. 3D integration tackles the physical problem by stacking active dies, turning long horizontal routes into short vertical jumps and placing memory directly above logic. However, an architectural problem remains: current products like HBM and AMD’s 3D V-Cache still rely on designs stubbornly rooted in 2D thinking.
This seminar challenges that flat paradigm. Starting with an overview of current 3D integration technologies and imec’s CMOS 2.0 roadmap, the presentation explores strategies for native 3D architectural co-design. To demonstrate these principles in action, a fundamentally 3D coarse-grained reconfigurable array (CGRA) utilizing LUT-based processing elements and stacked configuration memory will be introduced, highlighting how to finally think outside the 2D box.
27/11/2026 11:00 - 12:00
ESAT Aula R
