Time-interleaving architectures enable ultra-high-speed analog-to-digital conversion by operating many sub-ADCs in parallel, achieving a higher aggregate sampling rate. However, the resulting Signal-to-Noise-and-Distortion Ratio (SNDR) and Spurious-Free Dynamic Range (SFDR) are fundamentally bottlenecked by inter-channel mismatches. This seminar provides a mathematical characterization of these primary error sources alongside conventional mitigation strategies. The seminar will thereafter discuss a novel analog front-end architecture designed for inherent resistance to these inter-channel mismatches.
22/5/2026 11:00 - 12:00
ESAT Aula L
