Edge AI applications demand ultra-low-power and efficient computing solutions that can handle increasingly complex workloads under strict energy and area constraints. This thesis investigates low-energy DIMC techniques tailored for edge AI, addressing key design challenges across the circuit, architecture, and system levels. Two silicon-proven DIMC macro prototypes are presented, demonstrating effective techniques such as vertical p-sub layout, reverse precharge, and gray-code decoders for enhanced area and power efficiency. Building upon these, a DIMC-based system-on-chip (SoC), HUNBN, is designed for edge convolutional neural networks (CNNs). The SoC introduces innovations including split MAC workflows, efficient dataflow for sparse CNNs, and precision-scalable accumulation strategies. Measurement results confirm that the proposed DIMC architectures offer state-of-the-art energy efficiency (up to 23.8 TOPs/W) with compact SRAM area usage, outperforming prior art across multiple metrics. This work paves the way for scalable, energy-efficient edge intelligence using digital in-memory compute.
20/6/2025 13:00 - 15:00
ESAT Aula C, B91.300
