The demand for high-capacity and energy-efficient memory solutions has surged in the era of data-centric computing, particularly for Artificial Intelligence (AI) and Machine Learning (ML) workloads. In this seminar, I will introduce a novel memory architecture leveraging Charge-Coupled Device (CCD) technology, engineered in a sequential-access block memory configuration, to enhance Compute-near-Memory (CnM) systems. We propose an optimized 3D IGZO CCD block memory as an on-chip weight buffer for high-capacity CnM systems. Our approach achieves 2.95 − 131.26 x improvement in area efficiency and 1.32 − 4.33 x improvement in energy efficiency compared to SRAM solutions.
9/5/2025 - 9/3/2025
ESAT Aula R
