Design Optimization for Plasmonic Detectors

What

Rapidly evolving technology and the need for area-efficient RF-speed communication systems are pushing towards using CMOS comparators to maximize the speed with low power. Scaling the technology potentially helps here, but it involves a circuit-technology co-optimization. In this seminar, we focus on the design of such a comparator and buffer using IMEC sub-3nm technology. Simulation results indicate that the comparator can work at the targeted 200 GHz clock frequency, and the trade-offs between speed, energy, and circuit technique will be discussed.

When

9/2/2024 11:00 - 12:00

Where

ESAT Aula L