Event - 28 June 2024

Design of a Multi-Core Chip for Probabilistic AI

Lectured by Shirui Zhao

What

Real artificial intelligence requires the capability to perceive the environment and make decisions based on observations. Over the past few decades, perception tasks such as image/voice recognition have made significant progress thanks to deep learning models. However, Probabilistic Graphical Models (PMs), which can enhance machine learning with reasoning and decision-making abilities, require more attention.

To support more general PMs, sampling-based Markov Chain Monte Carlo (MCMC) algorithms are widely used to address the intractable problems. Unfortunately, MCMC is compute-intensive and challenging to parallelize, leading to inefficient execution on modern CPU/GPU platforms. Thus, we propose AIA, an Approximate Inference Accelerator, designed to accelerate inference of PMs at the edge.

AIA comprises a RISC-V host and a 2D mesh of 16 customized RISC-V cores optimized for efficient PM inference. Each core features: (i) a novel non-normalized Knuth-Yao sampler and interpolation unit, and (ii) core-to-core direct data access via the register file, which addresses compute-intensive operations. To fully exploit the parallel potential of MCMC algorithms, a customized compiler chain has been developed for effective spatial mapping and scheduling on the chip. AIA can generate 1277 MSamples/s at 0.9V and 20 GSamples/s/W at 0.7V, which is up to 2x faster and 1.45x more energy efficient compared to the previous state-of-the-art Markov Random Field (MRF) accelerator. We further demonstrate the flexibility of our design by mapping Bayesian Networks benchmarks onto AIA.

When

28/6/2024 11:00 - 12:00

Where

ESAT Aula L