Achieving efficient automation in hierarchical analog/mixed-signal (AMS) integrated circuit layout synthesis is challenging due to the vast design space and diverse layout requirements. Tools like ALIGN and MAGICAL-EDA address this using designer-extracted constraints, but as designs grow more complex, managing these constraints becomes problematic. Graph neural networks (GNNs) have been explored to extract inter-symmetry constraints in analog circuits, though with limited accuracy and scope for other constraint types in hierarchical AMS circuits.
In this seminar, I will present a generalized constraint learning and transfer (CLT) framework that can address a generalized, wider range of constraints and offers a more accurate and robust CLT methodology for hierarchical AMS circuit layout synthesis. A generate-and-aggregate approach enhanced by net-first GNN (Nest-GNN) and selective topological search (SelecTS) algorithms is introduced to accurately and efficiently learn and transfer to a more generalized range of constraint. Besides, an event timeline of 2024, summarizing the latest developments in AI4EDA domain, will also be explained to help the audience understand this research field better.
17/1/2025 11:00 - 12:00
ESAT 01.62
