In order to improve transistor performance from one generation to another, new materials and new device architectures are being continuously introduced (e.g., nano-sheet transistors). But with these innovations, new challenges appear for ensuring their reliability, i.e., limited degradation during operation. Up to now, reliability has been guaranteed at the technology level. Such approach is too restrictive, as it does not take into account the function of each transistor in the circuit. A reliability-aware circuit design, accounting for individual device degradation, should therefore be considered. Thorough, physics-based models are already being developed and improved for the various degradation mechanisms (such as Bias Temperature Instability, Hot Carrier Degradation, etc.) occurring in different regions of the FET {Vgate, Vdrain} operating space. However, to understand the impact of the degradation on circuits, the existing physical insights need to be converted to compact models usable in SPICE-level simulations. The objectives of this work, therefore are: i) converting the already-developed physical models into such reliability-aware compact models capable of describing the degradation of all major FET parameters, in the entire operating space as a function of an arbitrary stress history, ii) enabling computationally efficient simulations of FET degradation in various analog and digital circuits, and iii) validation of the compact models with measurements from real test circuits.
31/1/2025 11:00 - 12:00
ESAT Aula R
