The growing demand for higher data rates is pushing wireless communication towards higher frequencies, where wider bandwidths can support greater throughput. However, operating at mm-wave frequencies introduces significant challenges, including increased free-space path loss (FSPL) and difficulties in achieving high output power and efficiency. As a result, the FR3 frequency range is attracting interest as a promising compromise between available bandwidth and propagation losses for future 6G communication systems.
In this seminar, we will introduce the fundamental design considerations of RF power amplifiers and discuss the challenges associated with their implementation in CMOS technologies. Finally, we will present the design and measurement results of an FR3 power amplifier in 65 nm CMOS, which uses a balanced architecture and doubly adaptive biasing to maintain robust performance across a wide temperature range.
18/12/2026 11:00 - 12:00
ESAT B91.100
