Coarse‐grained reconfigurable arrays (CGRAs) offer a promising middle ground between fixed‐function ASICs and fully programmable FPGAs, delivering high performance and energy efficiency for diverse application domains. Yet, the inherent complexity of CGRA architectures—characterized by heterogeneous functional units, multi‐ported register files, and richly interconnected routing fabrics—poses significant challenges for automated mapping frameworks. In this seminar, we will dive into the world of spatial-temporal scheduling on the CGRA, targeting a suite of signal‐processing and machine‐learning kernels. By seamlessly combining the functional‐unit assignment, congestion‐aware routing, and parallelism-scheduling optimizations, our framework delivers robust, scalable CGRA mapping solutions adaptable to emerging architectures and application requirements.
20/6/2025 11:00 - 12:00
ESAT B91.200
