AMD XDNA NPUs are made of many small compute tiles, each with its own local memory, connected by a programmable on-chip network. This makes them well suited to LLM workloads: instead of repeatedly moving data to and from a large shared memory, computations can be arranged as a pipeline that streams data directly from one tile to the next.
The difficulty is deciding how to place computation and communication across the array. We present a compiler framework that automatically explores these spatial mappings and generates executable code. It achieves performance comparable to carefully hand-tuned implementations and can significantly reduce latency for fused LLM operators.
16/10/2026 11:00 - 12:00
ESAT B91.100
