To mitigate the diminishing gains in single-threaded CPU performance, modern processors have integrated vector extensions to accelerate parallel computations. While these extensions hold significant potential, compilers often struggle to consistently and effectively leverage them through automated techniques. The rapid rise of machine learning has further transformed the computational landscape, introducing advanced co-processors such as GPUs, Tensor Cores, and specialized accelerators. These devices offer very high computational performance but pose even greater challenges for automated utilization due to their complexity and specialized architectures.
This seminar dives deeper into the techniques for automatic code generation tailored to accelerators, exploring not only how compilers can adapt to leverage emerging hardware effectively but also how hardware can be designed to better support these advanced compiler strategies.
24/1/2025 11:00 - 12:00
ESAT Aula L
