Identifying the optimal circuit or architecture for a targeted application is a complex task due to the extensive manual design effort required. On one hand, the hardware performance can be heavily biased by parameters across different levels: from device-level transistor sizes and circuit-level topologies to system-level macro sizes. On the other hand, the optimal hardware choices vary depending on the optimization goals, such as energy efficiency or even carbon emission. These challenges necessitate fast, multi-target design space exploration (DSE) frameworks capable of assessing the impact of various parameters at different levels.
Machine learning and quantitative modeling are both promising methods for this purpose. While several previous seminars on machine learning-assisted DSE have shown its capability in analog circuit design, this seminar will demonstrate the capability of the quantitative modeling by using in-memory computing as the targeted hardware template. After validating against chip measurement results, the frameworks can identify the optimal hardware choices during the design phase by efficiently searching the parameter space, achieving over 100x speedup compared to traditional circuit-level simulation.
7/6/2024 11:00 - 12:00
ESAT Aula L
